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Viene del respositorio:
https://github.com/gundy/tinyfpga-bx-demos
En la definición de un coseno y seno así como todos los signed del modulo top dan error.
Código del seno
Código: Seleccionar todo
`ifndef __SINE_TABLE__
`define __SINE_TABLE__
module sine_table(
input clk,
input [7:0] idx,
output [15:0] val);
signed reg[15:0] SINE_TABLE_ROM[0:255];
initial $readmemh ("256x16_0.16_sine_table.mem", SINE_TABLE_ROM);
always @(posedge clk) begin
val <= SINE_TABLE_ROM[idx];
end
endmodule
`endif
Código: Seleccionar todo
Error (10170): Verilog HDL syntax error at sine_table.vh(9) near text: "signed"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
https://www.intel.com/content/www/us/en ... %3Aanswers
Pasado a Unamiga la demo: