cga_main Project Status (06/05/2021 - 07:18:46)
Project File: graphics-gremlin.xise Parser Errors: No Errors
Module Name: cga_main Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Timing Performance
  • Routing Results:
 
Design Strategy: Performance with Physical Synthesis
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 324 11,440 2%  
    Number used as Flip Flops 324      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 447 5,720 7%  
    Number used as logic 435 5,720 7%  
        Number using O6 output only 277      
        Number using O5 output only 59      
        Number using O5 and O6 99      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 12      
        Number with same-slice register load 8      
        Number with same-slice carry load 4      
        Number with other load 0      
Number of occupied Slices 181 1,430 12%  
Number of MUXCYs used 124 2,860 4%  
Number of LUT Flip Flop pairs used 523      
    Number with an unused Flip Flop 238 523 45%  
    Number with an unused LUT 76 523 14%  
    Number of fully used LUT-FF pairs 209 523 39%  
    Number of unique control sets 33      
    Number of slice register sites lost
        to control set restrictions
84 11,440 1%  
Number of bonded IOBs 85 102 83%  
    Number of LOCed IOBs 41 85 48%  
    IOB Flip Flops 37      
Number of RAMB16BWERs 1 32 3%  
Number of RAMB8BWERs 2 64 3%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 24 200 12%  
    Number used as ILOGIC2s 24      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 13 200 6%  
    Number used as OLOGIC2s 13      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.12      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentsá. 5. jun. 07:13:08 2021   
Translation ReportCurrentsá. 5. jun. 07:13:18 2021   
Map ReportCurrentsá. 5. jun. 07:14:12 2021   
Place and Route ReportCurrentsá. 5. jun. 07:14:26 2021   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentsá. 5. jun. 07:14:36 2021   
Bitgen ReportCurrentsá. 5. jun. 07:15:46 2021   
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportCurrentsá. 5. jun. 07:18:08 2021
WebTalk ReportCurrentsá. 5. jun. 07:18:46 2021
WebTalk Log FileCurrentsá. 5. jun. 07:18:48 2021

Date Generated: 06/05/2021 - 07:18:46