cga_main Project Status (06/05/2021 - 07:18:47)
Project File: graphics-gremlin.xise Parser Errors: No Errors
Module Name: mda_main Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
154 Warnings (120 new)
Design Goal: Timing Performance
  • Routing Results:
All Signals Completely Routed
Design Strategy: Performance with Physical Synthesis
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 217 11,440 1%  
    Number used as Flip Flops 217      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 338 5,720 5%  
    Number used as logic 332 5,720 5%  
        Number using O6 output only 213      
        Number using O5 output only 51      
        Number using O5 and O6 68      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 6      
        Number with same-slice register load 0      
        Number with same-slice carry load 6      
        Number with other load 0      
Number of occupied Slices 137 1,430 9%  
Number of MUXCYs used 96 2,860 3%  
Number of LUT Flip Flop pairs used 382      
    Number with an unused Flip Flop 193 382 50%  
    Number with an unused LUT 44 382 11%  
    Number of fully used LUT-FF pairs 145 382 37%  
    Number of unique control sets 18      
    Number of slice register sites lost
        to control set restrictions
63 11,440 1%  
Number of bonded IOBs 84 102 82%  
    Number of LOCed IOBs 41 84 48%  
    IOB Flip Flops 46      
Number of RAMB16BWERs 2 32 6%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 32 200 16%  
    Number used as ILOGIC2s 32      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 14 200 7%  
    Number used as OLOGIC2s 14      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.89      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentsá. 5. jun. 07:17:16 20210152 Warnings (119 new)13 Infos (11 new)
Translation ReportCurrentsá. 5. jun. 07:17:26 2021000
Map ReportCurrentsá. 5. jun. 07:18:08 202101 Warning (1 new)9 Infos (2 new)
Place and Route ReportCurrentsá. 5. jun. 07:18:22 202101 Warning (0 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentsá. 5. jun. 07:18:30 2021004 Infos (0 new)
Bitgen ReportCurrentsá. 5. jun. 07:18:46 2021000
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportCurrentsá. 5. jun. 07:18:08 2021
WebTalk ReportCurrentsá. 5. jun. 07:18:46 2021
WebTalk Log FileCurrentsá. 5. jun. 07:18:48 2021

Date Generated: 06/05/2021 - 07:18:47