Project Statistics |
PROPEXT_MapGlobalOptimization_spartan6=Speed |
PROPEXT_xilxMapPackRegInto_spartan6=For Inputs and Outputs |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_ISimsUseCustomWaveConfigFile_behav=true |
PROP_LastAppliedGoal=Timing Performance |
PROP_LastAppliedStrategy=Performance with Physical Synthesis;C:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_performance_with_physicalsynthesis.xds |
PROP_ManualCompileOrderImp=false |
PROP_MapLogicOptimization_spartan6=true |
PROP_MapPlacerCostTable_spartan6=75 |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/tb_sdtest |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthFsmEncode=None |
PROP_SynthOptEffort_spartan6=High |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2016-08-15T01:00:41 |
PROP_intWbtProjectID=1ADB14887422404EB52F1055BCCEAB3A |
PROP_intWbtProjectIteration=2 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.tb_sdtest |
PROP_xilxBitgStart_IntDone=true |
PROP_xilxSynthRegBalancing=Yes |
PROP_xstPackIORegister=Yes |
PROP_xstWriteTimingConstraints=true |