Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) 5dbf4ffd3e794df1991eabcc929970a9.1ADB14887422404EB52F1055BCCEAB3A.2 Target Package: tqg144
Registration ID 211847159_0_0_350 Target Speed: -2
Date Generated 2021-06-05T07:18:44 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz CPU Speed 2400 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz CPU Speed 2400 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=1
  • 14-bit up accumulator=1
Adders/Subtractors=5
  • 14-bit adder=2
  • 5-bit adder=1
  • 8-bit adder=1
  • 9-bit adder=1
Comparators=16
  • 14-bit comparator equal=1
  • 32-bit comparator greater=1
  • 4-bit comparator equal=1
  • 5-bit comparator equal=2
  • 5-bit comparator greater=3
  • 5-bit comparator lessequal=2
  • 7-bit comparator equal=1
  • 8-bit comparator equal=2
  • 8-bit comparator not equal=1
  • 9-bit comparator equal=1
  • 9-bit comparator not equal=1
Counters=8
  • 24-bit up counter=1
  • 3-bit up counter=1
  • 32-bit up counter=1
  • 4-bit up counter=2
  • 5-bit up counter=3
Multiplexers=38
  • 1-bit 12-to-1 multiplexer=1
  • 1-bit 2-to-1 multiplexer=9
  • 14-bit 2-to-1 multiplexer=2
  • 19-bit 2-to-1 multiplexer=3
  • 3-bit 2-to-1 multiplexer=5
  • 8-bit 2-to-1 multiplexer=18
RAMs=2
  • 4096x8-bit single-port block Read Only RAM=1
  • 4x12-bit single-port distributed Read Only RAM=1
Registers=236
  • Flip-Flops=236
Xors=1
  • 1-bit xor2=1
MiscellaneousStatistics
  • AGG_BONDED_IO=84
  • AGG_IO=84
  • AGG_LOCED_IO=41
  • AGG_SLICE=137
  • NUM_BONDED_IOB=84
  • NUM_BSFULL=145
  • NUM_BSLUTONLY=193
  • NUM_BSREGONLY=44
  • NUM_BSUSED=382
  • NUM_BUFG=2
  • NUM_BUFIO2=1
  • NUM_BUFIO2FB=1
  • NUM_ILOGIC2=32
  • NUM_IOB_FF=46
  • NUM_LOCED_IOB=41
  • NUM_LOGIC_O5ANDO6=68
  • NUM_LOGIC_O5ONLY=51
  • NUM_LOGIC_O6ONLY=213
  • NUM_LUT_RT_DRIVES_CARRY4=6
  • NUM_LUT_RT_EXO6=6
  • NUM_LUT_RT_O5=1
  • NUM_LUT_RT_O6=51
  • NUM_OLOGIC2=14
  • NUM_PLL_ADV=1
  • NUM_RAMB16BWER=2
  • NUM_SLICEL=28
  • NUM_SLICEX=109
  • NUM_SLICE_CARRY4=24
  • NUM_SLICE_CONTROLSET=18
  • NUM_SLICE_CYINIT=464
  • NUM_SLICE_F7MUX=4
  • NUM_SLICE_FF=217
  • NUM_SLICE_UNUSEDCTRL=65
  • NUM_UNUSABLE_FF_BELS=63
NetStatistics
  • NumNets_Active=667
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=5
  • NumNodesOfType_Active_BOUNCEIN=46
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=9
  • NumNodesOfType_Active_BUFIOINP=2
  • NumNodesOfType_Active_CLKPIN=88
  • NumNodesOfType_Active_CLKPINFEED=15
  • NumNodesOfType_Active_CNTRLPIN=79
  • NumNodesOfType_Active_DOUBLE=703
  • NumNodesOfType_Active_GENERIC=146
  • NumNodesOfType_Active_GLOBAL=58
  • NumNodesOfType_Active_INPUT=48
  • NumNodesOfType_Active_IOBIN2OUT=134
  • NumNodesOfType_Active_IOBOUTPUT=133
  • NumNodesOfType_Active_LUTINPUT=1286
  • NumNodesOfType_Active_OUTBOUND=596
  • NumNodesOfType_Active_OUTPUT=487
  • NumNodesOfType_Active_PADINPUT=61
  • NumNodesOfType_Active_PADOUTPUT=40
  • NumNodesOfType_Active_PINBOUNCE=246
  • NumNodesOfType_Active_PINFEED=1570
  • NumNodesOfType_Active_PINFEED2=39
  • NumNodesOfType_Active_QUAD=864
  • NumNodesOfType_Active_REGINPUT=66
  • NumNodesOfType_Active_SINGLE=840
  • NumNodesOfType_Gnd_BOUNCEIN=15
  • NumNodesOfType_Gnd_CNTRLPIN=1
  • NumNodesOfType_Gnd_DOUBLE=7
  • NumNodesOfType_Gnd_GENERIC=13
  • NumNodesOfType_Gnd_HGNDOUT=10
  • NumNodesOfType_Gnd_INPUT=20
  • NumNodesOfType_Gnd_IOBIN2OUT=13
  • NumNodesOfType_Gnd_IOBOUTPUT=13
  • NumNodesOfType_Gnd_OUTBOUND=8
  • NumNodesOfType_Gnd_OUTPUT=10
  • NumNodesOfType_Gnd_PADINPUT=13
  • NumNodesOfType_Gnd_PINBOUNCE=18
  • NumNodesOfType_Gnd_PINFEED=29
  • NumNodesOfType_Gnd_REGINPUT=5
  • NumNodesOfType_Gnd_SINGLE=9
  • NumNodesOfType_Vcc_GENERIC=2
  • NumNodesOfType_Vcc_HVCCOUT=45
  • NumNodesOfType_Vcc_IOBIN2OUT=2
  • NumNodesOfType_Vcc_IOBOUTPUT=2
  • NumNodesOfType_Vcc_LUTINPUT=120
  • NumNodesOfType_Vcc_PADINPUT=2
  • NumNodesOfType_Vcc_PINFEED=122
SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=43
  • IOB-IOBS=41
  • SLICEL-SLICEM=14
  • SLICEX-SLICEL=15
  • SLICEX-SLICEM=34
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • BUFIO2=1
  • BUFIO2FB=1
  • BUFIO2FB_BUFIO2FB=1
  • BUFIO2_BUFIO2=1
  • CARRY4=24
  • FF_SR=30
  • HARD0=37
  • HARD1=1
  • ILOGIC2=32
  • ILOGIC2_IFF=32
  • IOB=84
  • IOB_IMUX=40
  • IOB_INBUF=40
  • IOB_OUTBUF=60
  • LUT5=120
  • LUT6=338
  • OLOGIC2=14
  • OLOGIC2_OUTFF=14
  • PAD=84
  • PLL_ADV=1
  • PLL_ADV_PLL_ADV=1
  • RAMB16BWER=2
  • RAMB16BWER_RAMB16BWER=2
  • REG_SR=187
  • SELMUX2_1=67
  • SLICEL=28
  • SLICEX=109
 
Configuration Data
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
FF_SR
  • CK=[CK:30] [CK_INV:0]
  • SRINIT=[SRINIT0:26] [SRINIT1:4]
  • SYNC_ATTR=[ASYNC:27] [SYNC:3]
ILOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:32]
ILOGIC2_IFF
  • CLK0=[CLK0_INV:0] [CLK0:32]
  • IFFTYPE=[FF:32]
  • SRINIT_Q=[0:30] [1:2]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:60]
  • SLEW=[SLOW:59] [FAST:1]
  • SUSPEND=[3STATE:60]
OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:14]
OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:14]
  • OUTFFTYPE=[FF:14]
  • SRINIT_OQ=[0:14]
PLL_ADV
  • RST=[RST:1] [RST_INV:0]
PLL_ADV_PLL_ADV
  • BANDWIDTH=[OPTIMIZED:1]
  • CLK_FEEDBACK=[CLKFBOUT:1]
  • COMPENSATION=[SYSTEM_SYNCHRONOUS:1]
  • PLL_ADD_LEAKAGE=[2:1]
  • PLL_AVDD_COMP_SET=[2:1]
  • PLL_CLAMP_BYPASS=[FALSE:1]
  • PLL_CLAMP_REF_SEL=[1:1]
  • PLL_CLK0MX=[0:1]
  • PLL_CLK1MX=[0:1]
  • PLL_CLK2MX=[0:1]
  • PLL_CLK3MX=[0:1]
  • PLL_CLK4MX=[0:1]
  • PLL_CLK5MX=[0:1]
  • PLL_CLKBURST_CNT=[0:1]
  • PLL_CLKBURST_ENABLE=[TRUE:1]
  • PLL_CLKCNTRL=[0:1]
  • PLL_CLKFBMX=[0:1]
  • PLL_CLKFBOUT2_EDGE=[TRUE:1]
  • PLL_CLKFBOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKFBOUT_EDGE=[TRUE:1]
  • PLL_CLKFBOUT_EN=[FALSE:1]
  • PLL_CLKFBOUT_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT0_EDGE=[TRUE:1]
  • PLL_CLKOUT0_EN=[FALSE:1]
  • PLL_CLKOUT0_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT1_EDGE=[TRUE:1]
  • PLL_CLKOUT1_EN=[FALSE:1]
  • PLL_CLKOUT1_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT2_EDGE=[TRUE:1]
  • PLL_CLKOUT2_EN=[FALSE:1]
  • PLL_CLKOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT3_EDGE=[TRUE:1]
  • PLL_CLKOUT3_EN=[FALSE:1]
  • PLL_CLKOUT3_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT4_EDGE=[TRUE:1]
  • PLL_CLKOUT4_EN=[FALSE:1]
  • PLL_CLKOUT4_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT5_EDGE=[TRUE:1]
  • PLL_CLKOUT5_EN=[FALSE:1]
  • PLL_CLKOUT5_NOCOUNT=[TRUE:1]
  • PLL_CLK_LOST_DETECT=[FALSE:1]
  • PLL_CP=[1:1]
  • PLL_CP_BIAS_TRIP_SHIFT=[TRUE:1]
  • PLL_CP_REPL=[1:1]
  • PLL_CP_RES=[0:1]
  • PLL_DIRECT_PATH_CNTRL=[TRUE:1]
  • PLL_DIVCLK_EDGE=[TRUE:1]
  • PLL_DIVCLK_NOCOUNT=[TRUE:1]
  • PLL_DVDD_COMP_SET=[2:1]
  • PLL_EN=[FALSE:1]
  • PLL_EN_DLY=[TRUE:1]
  • PLL_EN_LEAKAGE=[2:1]
  • PLL_EN_TCLK0=[TRUE:1]
  • PLL_EN_TCLK1=[TRUE:1]
  • PLL_EN_TCLK2=[TRUE:1]
  • PLL_EN_TCLK3=[TRUE:1]
  • PLL_EN_VCO0=[FALSE:1]
  • PLL_EN_VCO1=[FALSE:1]
  • PLL_EN_VCO2=[FALSE:1]
  • PLL_EN_VCO3=[FALSE:1]
  • PLL_EN_VCO4=[FALSE:1]
  • PLL_EN_VCO5=[FALSE:1]
  • PLL_EN_VCO6=[FALSE:1]
  • PLL_EN_VCO7=[FALSE:1]
  • PLL_EN_VCO_DIV1=[FALSE:1]
  • PLL_EN_VCO_DIV6=[TRUE:1]
  • PLL_INTFB=[0:1]
  • PLL_IO_CLKSRC=[0:1]
  • PLL_LFHF=[3:1]
  • PLL_LOCK_FB_DLY=[3:1]
  • PLL_LOCK_REF_DLY=[5:1]
  • PLL_MAN_LF_EN=[TRUE:1]
  • PLL_NBTI_EN=[TRUE:1]
  • PLL_PFD_CNTRL=[8:1]
  • PLL_PFD_DLY=[1:1]
  • PLL_PWRD_CFG=[FALSE:1]
  • PLL_REG_INPUT=[TRUE:1]
  • PLL_RES=[1:1]
  • PLL_SEL_SLIPD=[FALSE:1]
  • PLL_SKEW_CNTRL=[0:1]
  • PLL_TEST_IN_WINDOW=[FALSE:1]
  • PLL_VDD_SEL=[0:1]
  • PLL_VLFHIGH_DIS=[TRUE:1]
  • RST=[RST:1] [RST_INV:0]
RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • DATA_WIDTH_A=[4:2]
  • DATA_WIDTH_B=[0:2]
  • DOA_REG=[0:2]
  • DOB_REG=[0:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • EN_RSTRAM_A=[TRUE:2]
  • EN_RSTRAM_B=[TRUE:2]
  • RAM_MODE=[TDP:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTTYPE=[SYNC:2]
  • RST_PRIORITY_A=[CE:2]
  • RST_PRIORITY_B=[CE:2]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WRITE_MODE_A=[WRITE_FIRST:2]
  • WRITE_MODE_B=[WRITE_FIRST:2]
REG_SR
  • CK=[CK:187] [CK_INV:0]
  • LATCH_OR_FF=[FF:187]
  • SRINIT=[SRINIT0:178] [SRINIT1:9]
  • SYNC_ATTR=[ASYNC:161] [SYNC:26]
SLICEL
  • CLK=[CLK:6] [CLK_INV:0]
SLICEX
  • CLK=[CLK:66] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
BUFIO2
  • DIVCLK=1
  • I=1
BUFIO2FB
  • I=1
  • O=1
BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
CARRY4
  • CIN=18
  • CO1=1
  • CO2=1
  • CO3=19
  • CYINIT=6
  • DI0=24
  • DI1=21
  • DI2=19
  • DI3=18
  • O0=20
  • O1=20
  • O2=17
  • O3=17
  • S0=24
  • S1=24
  • S2=20
  • S3=20
FF_SR
  • CE=16
  • CK=30
  • D=30
  • Q=30
  • SR=3
HARD0
  • 0=37
HARD1
  • 1=1
ILOGIC2
  • CE0=31
  • CLK0=32
  • D=32
  • FABRICOUT=31
  • Q4=32
ILOGIC2_IFF
  • CE0=31
  • CLK0=32
  • D=32
  • Q1=32
IOB
  • I=40
  • O=60
  • PAD=84
  • T=16
IOB_IMUX
  • I=40
  • OUT=40
IOB_INBUF
  • OUT=40
  • PAD=40
IOB_OUTBUF
  • IN=60
  • OUT=60
  • TRI=16
LUT5
  • A1=21
  • A2=43
  • A3=52
  • A4=30
  • A5=51
  • O5=120
LUT6
  • A1=103
  • A2=149
  • A3=206
  • A4=252
  • A5=317
  • A6=333
  • O6=338
OLOGIC2
  • CLK0=14
  • D1=14
  • OCE=8
  • OQ=14
OLOGIC2_OUTFF
  • CE=8
  • CK0=14
  • D1=14
  • Q=14
PAD
  • PAD=84
PLL_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKOUT1=1
  • RST=1
PLL_ADV_PLL_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKOUT1=1
  • RST=1
RAMB16BWER
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=2
  • ADDRA3=2
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • CLKA=2
  • DIA0=2
  • DIA1=2
  • DIA2=2
  • DIA3=2
  • DOA0=2
  • DOA1=2
  • DOA2=2
  • DOA3=2
  • ENA=2
  • REGCEA=2
  • RSTA=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
RAMB16BWER_RAMB16BWER
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=2
  • ADDRA3=2
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • CLKA=2
  • DIA0=2
  • DIA1=2
  • DIA2=2
  • DIA3=2
  • DOA0=2
  • DOA1=2
  • DOA2=2
  • DOA3=2
  • ENA=2
  • REGCEA=2
  • RSTA=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
REG_SR
  • CE=89
  • CK=187
  • D=187
  • Q=187
  • SR=26
SELMUX2_1
  • 0=67
  • 1=4
  • OUT=67
  • S0=67
SLICEL
  • A=2
  • A1=5
  • A2=7
  • A3=9
  • A4=12
  • A5=25
  • A6=27
  • AMUX=19
  • AQ=4
  • AX=3
  • B=3
  • B1=6
  • B2=8
  • B3=9
  • B4=11
  • B5=23
  • B6=26
  • BMUX=20
  • BQ=2
  • BX=5
  • C1=7
  • C2=9
  • C3=9
  • C4=10
  • C5=21
  • C6=23
  • CE=2
  • CIN=18
  • CLK=6
  • CMUX=20
  • COUT=18
  • CQ=2
  • CX=7
  • D1=7
  • D2=9
  • D3=9
  • D4=10
  • D5=20
  • D6=23
  • DMUX=17
  • DQ=1
  • DX=3
  • SR=2
SLICEX
  • A=34
  • A1=37
  • A2=47
  • A3=57
  • A4=66
  • A5=70
  • A6=71
  • AMUX=14
  • AQ=56
  • AX=16
  • B=28
  • B1=16
  • B2=29
  • B3=42
  • B4=49
  • B5=53
  • B6=56
  • BMUX=11
  • BQ=43
  • BX=14
  • C=21
  • C1=13
  • C2=26
  • C3=42
  • C4=47
  • C5=52
  • C6=54
  • CE=28
  • CLK=66
  • CMUX=14
  • CQ=45
  • CX=11
  • D=33
  • D1=21
  • D2=36
  • D3=44
  • D4=47
  • D5=53
  • D6=53
  • DMUX=11
  • DQ=34
  • DX=12
  • SR=8
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt on -ol high -xe n -t 75 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt 2 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 1 1 0 0 0 0 0
bitgen 224 224 0 0 0 0 0
map 261 223 0 0 0 0 0
netgen 2 2 0 0 0 0 0
ngcbuild 2 2 0 0 0 0 0
ngdbuild 278 273 0 0 0 0 0
par 223 223 0 0 0 0 0
trce 222 222 0 0 0 0 0
xps 1 1 0 0 0 0 0
xst 517 506 0 0 0 0 0
 
Project Statistics
PROPEXT_MapGlobalOptimization_spartan6=Speed PROPEXT_xilxMapPackRegInto_spartan6=For Inputs and Outputs
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_ISimsUseCustomWaveConfigFile_behav=true PROP_LastAppliedGoal=Timing Performance
PROP_LastAppliedStrategy=Performance with Physical Synthesis;C:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_performance_with_physicalsynthesis.xds PROP_ManualCompileOrderImp=false
PROP_MapLogicOptimization_spartan6=true PROP_MapPlacerCostTable_spartan6=75
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/tb_sdtest
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthFsmEncode=None
PROP_SynthOptEffort_spartan6=High PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2016-08-15T01:00:41 PROP_intWbtProjectID=1ADB14887422404EB52F1055BCCEAB3A
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.tb_sdtest
PROP_xilxBitgStart_IntDone=true PROP_xilxSynthRegBalancing=Yes
PROP_xstPackIORegister=Yes PROP_xstWriteTimingConstraints=true
 
Core Statistics
Core Type=clk_wiz_v3_6
clkin1_period=20.0 clkin2_period=20.0 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=2 primtype_sel=PLL_BASE
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=false use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=false
use_status=false
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_FD=59 NGDBUILD_NUM_FDE=127 NGDBUILD_NUM_FDR=37
NGDBUILD_NUM_FDRE=40 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=23 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=12 NGDBUILD_NUM_IOBUF=16 NGDBUILD_NUM_LUT1=62 NGDBUILD_NUM_LUT2=46
NGDBUILD_NUM_LUT3=66 NGDBUILD_NUM_LUT4=36 NGDBUILD_NUM_LUT5=46 NGDBUILD_NUM_LUT6=86
NGDBUILD_NUM_MUXCY=90 NGDBUILD_NUM_MUXF7=3 NGDBUILD_NUM_OBUF=44 NGDBUILD_NUM_RAMB16BWER=2
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=75
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_FD=59 NGDBUILD_NUM_FDE=127 NGDBUILD_NUM_FDR=37
NGDBUILD_NUM_FDRE=40 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=39 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=12 NGDBUILD_NUM_LUT1=62 NGDBUILD_NUM_LUT2=46 NGDBUILD_NUM_LUT3=66
NGDBUILD_NUM_LUT4=36 NGDBUILD_NUM_LUT5=46 NGDBUILD_NUM_LUT6=86 NGDBUILD_NUM_MUXCY=90
NGDBUILD_NUM_MUXF7=3 NGDBUILD_NUM_OBUF=44 NGDBUILD_NUM_OBUFT=16 NGDBUILD_NUM_PLL_ADV=1
NGDBUILD_NUM_RAMB16BWER=2 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=75
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-2-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=2 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=YES -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=NO -fsm_style=LUT -ram_extract=Yes
-ram_style=Auto -rom_extract=Yes -shreg_extract=YES -rom_style=Auto
-auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto
-iobuf=YES -max_fanout=100000 -bufg=16 -register_duplication=YES
-register_balancing=Yes -move_first_stage=YES -move_last_stage=YES -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=True
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5