hello_world Project Status (12/19/2018 - 23:15:18)
Project File:	test2.xise	Parser Errors:	No Errors
Module Name:	hello_world	Implementation State:	Programming File Generated
Target Device:	xc3s1600e-5fg320	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	1 Warning (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	26	29,504	1%
Number of 4 input LUTs	7	29,504	1%
Number of occupied Slices	18	14,752	1%
Number of Slices containing only related logic	18	18	100%
Number of Slices containing unrelated logic	0	18	0%
Total Number of 4 input LUTs	32	29,504	1%
Number used as logic	7
Number used as a route-thru	25
Number of bonded IOBs	4	250	1%
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	2.26

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Wed Dec 19 23:29:23 2018	0	0	0
Translation Report	Current	Wed Dec 19 23:29:29 2018	0	0	0
Map Report	Current	Wed Dec 19 23:29:34 2018	0	0	2 Infos (0 new)
Place and Route Report	Current	Wed Dec 19 23:29:51 2018	0	1 Warning (0 new)	2 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Wed Dec 19 23:29:55 2018	0	0	6 Infos (0 new)
Bitgen Report	Current	Wed Dec 19 23:30:06 2018	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Wed Dec 19 23:30:07 2018
WebTalk Log File	Current	Wed Dec 19 23:30:10 2018

Date Generated: 12/21/2018 - 11:36:39